1. Field of the Invention
This invention relates to a method and structure in the manufacture of semiconductor memory devices, and more particularly to method and structure of manufacture of mask ROM memory devices.
2. Description of the Prior Art
A memory device is widely used in the information industry, and is particularly used in microprocessors and computers. In order to achieve a faster speed of information exchange with a tremendous quantity, the information product needs the properties that are necessarily small in size and a reduced weight. Besides, the program and operation performed the software has become complicated in the recent years so that the properties are necessarily manufacturing a memory with a higher memory capacity and faster access speed. Therefore, a mask ROM with higher memory capacity, higher integrity and faster access speed is currently a common memory structure.
However, when the dimension of the mask ROM device goes below 0.35 microns or smaller, a gap between 0 to 1 has become smaller in the electricity because of the device margin and narrower line width. Hence, the demanded process window is also getting smaller. When the process with the bigger dimension of the device is completely imitated to a smaller dimension, it could not get a preferred yield due to different properties and different structure with Inter-Layer Dielectric (ILD) between two products.
FIG. 1A to FIG. 1D is the method and structure of manufacture in conventional mask ROM memory devices 100. Referring to FIG. 1A, providing a semiconductor substrate 101 firstly, such as P type silicon substrate, wherein the semiconductor substrate 101 comprises a plurality of buried N+ bit lines 103 therein. Next, a gate oxide layer 105 and a plurality of polysilicon word lines 107 are respectively formed on the semiconductor substrate 101. Then, an inter layer dielectric 109, the material could be Borophosphosilicate Glass (BPSG), is formed on the polysilicon word lines 107. After that, forming a glue layer 111 on the inter layer dielectric 109.
Following that, referring to FIG. 1B, forming a photoresist layer 113 on the glue layer 111, and performing a photolithography and etching process to the photoresist layer 113 in order to form a first opening 112 therein. The photoresist layer 113 having a first opening 112 is formed on the surface of the glue layer 111.
Subsequently, referring to FIG. 1C, utilizing the photoresist layer 113 having a first opening 112 as a photomask and then performing a dry etching process in the glue layer 111. Therefore, the second opening 115 are formed on the surface of the inter layer dielectric (ILD) 109 and within the glue layer 111. Next, removing the photoresist layer 113. Then, performing a step of ion implantation 117 in the mask ROM device 100 so as to form the code areas 119 within the semiconductor substrate 101.
Continue referring to FIG. 1C, as a result it has to etch the glue layer 111 before forming the code areas 119 in the mask ROM device 100, though the inter layer dielectric 109 which is an oxide layer below the glue layer 111. Hence, etching the glue layer 111 will have a phenomenon of over etching within the inter layer dielectric 109, which could not precisely control the thickness of the inter layer dielectric 109 after each etching. Moreover, the etching process will also produce a profile with bevels in the inter layer dielectric 109. For that reason; the phenomenon of over etching and the profile with bevels in the inter layer dielectric 109 will influence the implanted profile and implanted depth of the code areas 119 in the semiconductor substrate 101 when ion implanting in the mask ROM device 100. Also, the threshold voltage of the mask ROM device 100 is decided by the implanted ion concentration so that the profile with bevels and the phenomenon of over etching will cause the implanted ion distribute non-uniformly. Therefore, it causes the electricity unstably in the mask ROM device 100; moreover, the yield will also be influenced.
In addition, due to the fact that the etching process to the mask ROM device 100 is performed first, and then the implantation of ROM code, which decides the order-form from the users. However, the second opening 115 is accessible to oxidize so as to form an oxide layer on the surface while waiting for an order-form. (Because the bottom of the second opening 115 is an inter layer dielectric 109) Therefore, after receiving the order-form from users, it has to perform an etching or cleaning process to the second opening 115 so as to remove the oxide layer, which is formed already. Then, performing the ion implantation following that, so the manufacturing time and manufacturing cost will be improved.
Still, after accomplishing the etching process to the glue layer 111, the second opening 115 produced therein has a negative bias with a critical dimension. Thus, in order to maintain the critical dimensional after the etch inspection as the same as the photomasks critical dimensional after etching the glue layer 111(it means to broaden the code areas 119), the post exposure process of the photoresist layer 113 has to be preformed when doing the photolithography process. However, the patterned photoresist layer and the non-patterned photoresist layer are exited simultaneously on the photoresist layer 113 (the patterned photoresist layer with respects to the implant region, the non-patterned photoresist layer with respects to the non-implant region). Therefore, the process window of the photoresist layer, which is above the non-implant region will be influenced and reduced, even vanished during the post exposure process. This situation will make the device 10 inaccurate with electricity.
Finally, referring to FIG. 1D, utilizing a sputtering method to form a blanket layer of metal 121, which uses as an electric connection with the polysilicon word lines 107, on the mask ROM device 100 and down to the code areas 119.
As mentioned above the process of the conventional mask ROM, the conventional mask ROM device has problems with inaccuracy and unstability in the electricity because etching the glue layer and post exposing to the photoresist layer. Hence, a method of manufacture of mask ROM memory devices is required to overcome the problems of the process in the prior art.